I/O blocks used in PLDs provide the interface between external integrated circuit package pins and the internal logic, and are user-configurable. Each I/O block controls one package pin, hence one pad of the integrated circuit die, and can be defined for input, output or bidirectional signals.
FIG. 1(A) depicts a prior art I/O block which is defined as an input block with invert/register/latch capability. In FIG. 1(A), the input register IR (dotted line) consists of two stages ML and SL. ML represents a master latch and SL represents a slave latch. (A latch is a device which in a transparent mode forwards input data to its output and in a latched mode presents at its output a signal which was present at its input when the latch switched modes. Two latches in series which are always in opposite modes form a flip flop or register.) M1-M3 represent multiplexers or signal path selectors. Configuration bits CB0-CB3, which may come from a conventional configuration register (not shown) determine which input path of the multiplexers will go to the output thereof respectively. Configuration bit CB3 forms one of the two inputs of gate XOR1, and the other input of gate XOR1 is the input data coming from the PAD. Configuration bit CB3 determines whether the input data is to be inverted or not before entering the latches. When CB3 is logic value "1", the output of gate XOR1 is inverted input data, while when CB3 is logic value "0" the output of the gate XOR1 is in phase with the input data (non-inverted). The logic function of gate XOR1 is shown in the truth table of FIG. 1(B), which shows the inversion selection of the input data by configuration bit CB3. Global clocks CLK1 and CLK0 are typically connected to alternative sources of clock signals, for example an external clock signal which is distributed globally through the chip, and an internal clock signal which may be distributed globally or may be a different signal for different parts of the chip. Internal clock signals in a device which includes programmable macrocells or logic blocks may be generated by one of these programmable macrocells or logic blocks and used as a clock signal for controlling other macrocells or logic blocks.
FIG. 1(C) shows the functions of the register under four different combinations of configuration bits CB0 and CB1. When both CB0 and CB1=0, the state of the master and slave latches (the values in their Q outputs) follow their D inputs (the register is transparent). When CB0=1 and CB1=0 the master latch is always transparent and the slave latch responds to the clock signal as follows: when the clock signal is low, the slave latch provides on its output the value of the input present when the clock signal goes from high to low; when the clock signal is high, the slave latch passes its input signal to its output. When CB0=0 and CB1=1, the slave latch is always transparent and the master latch latches its input every time the clock pulse rises from low to high level. The register is referred to as being in a negative-enabled-latch mode. The other instance is CB0=1 and CB1=1, when the register is in a positive-edge-triggered mode. In this mode, the master latch latches its input (i.e., the output of gate XOR1 at the rising edge of the clock signal (clock signal is selected by CB2), and the slave latch latches the output state of the master latch at the falling edge of the clock signal.
This input register/latch is used as a storage register that is connected to a bus, with a data strobe used as a clock signal to control when the data should be registered. However, it is awkward to achieve a desired register control when the register is directly controlled by clock signals because the register accepts new data unconditionally on each clock cycle. The device needs increased flexibility.